Integrated circuits or chips may include a large number of interconnected transistors. The transistors and other circuit elements are interconnected in various ways to provide desired circuit functions. It is usually most efficient to fabricate multiple integrated circuits on a single wafer. After processing, the integrated circuits that are fabricated on the wafer are separated and then packaged. The wafer can accommodate a fixed number of integrated circuits for a given integrated circuit size. Reducing the size of individual transistors in the integrated circuit may help to reduce the overall size of the integrated circuit. This, in turn, allows an increased number of integrated circuits or chips to be made on each wafer and reduces the cost of the integrated circuits.
Referring now to FIGS. 1 and 2, an exemplary transistor 10 includes a drain 12, a gate 14, a source 16 and a body 18 or substrate tap. For example, the transistor 10 in FIG. 1 is an NMOS transistor. In some circumstances, the body 18 is connected to the source 16 as shown in FIG. 2.
Referring now to FIG. 3, the body 18 includes a p+ region and may include a contact tap 30. The source 16 includes an n+ region and may include a contact tap 32. The drain 12 includes an n+ region and may include a contact tap 34. Additional transistors may be fabricated on one or sides of the transistor 10 as indicated by “ . . . ” in FIG. 3.
Referring now to FIG. 4, the body 18 may be repeated between sources 16 of adjacent transistors. The body 18 takes up valuable chip area and increases the size of the transistor and the integrated circuit. Additional transistors can be arranged on one or more sides of the transistor 10 as shown by “ . . . ” in FIG. 4.